With the rise of the modern digital age, semiconductor memory devices are becoming more and more integrated into people's everyday lives. Such memory devices store digitally encoded data for personal computers, communication devices, music players, image processors, automotive systems, and the like.
FIG. 1 illustrates a portion of a conventional memory device 100 that includes a memory array 102, which is made up of a number of memory cells 104 arranged in M rows (e.g., words) and N columns (e.g., bits), wherein the individual memory cells 104 are labeled as CROW-COLUMN for clarity in FIG. 1. Along each row, a wordline is coupled to respective gates of respective access transistors (not shown) within respective memory cells. For example, in Row 1, wordline WL1 is coupled to respective gates of respective access transistors for memory cells C1-1 through C1-N; in Row 2, wordline WL2 is coupled to respective gates of respective access transistors for memory cells C2-1 though C2-N; and so on. Along each column, a pair of complementary bitlines can be coupled to complementary storage nodes of respective memory cells. For example, for Column 1, complementary bitlines BL1, BL1′ can be coupled to respective complementary storage nodes of memory cells C1-1 though CM-1; for column 2, complementary bitlines BL2, BL2′ can be coupled to respective complementary storage nodes of memory cells C1-2 though CM-2; and so on. Other architectures, such as Flash memory or dynamic random access memory (DRAM) for example, can include a single-ended bitline for each column, as opposed to the complementary bitlines shown in FIG. 1.
To facilitate read operations, sense amps 106 can be coupled to respective columns of memory cells. Each sense amp 106 has a sense line SL and a reference sense line SL′. For example, in the first column in the architecture shown in FIG. 1, sense amp SA-C1 has a sense line SL1 coupled to bitline BL1 and has a reference sense line SL1′ coupled to complementary bitline BL1′. In other embodiments, such as a DRAM or flash memory architecture where the cell has only a single bitline and no complementary bitline, the reference senseline SL′ can be coupled to a reference cell or some other reference potential.
To read data values from a row of memory cells, the wordline of the row is asserted to establish respective differential biases on the senselines and reference senselines, wherein the differential bias seen by each sense amp depends on the data state read from the corresponding memory cell. For example, if cell C1-1 stores a logical “1” value and C1-2 stores a logical “0” value, assertion of wordline WL1 can lead to a first differential bias on SL1/SL1′ (corresponding to a logical “1” which can be detected by sense amp SA-C1) and can concurrently lead to a second, different differential bias on SL2/SL2′ (corresponding to a logical “0” which can be detected by sense amp SA-C2). After the sense amps 106 detect the respective differential biases, the sense amps 106 then latch the corresponding data values and another read or write operation can occur.
Although memory devices and sense amplifiers are well known, memory designers are constantly striving to provide faster and more accurate read and write operations so that data can be retrieved and/or processed more quickly. For read operations, the time required for pre-charging of the bitlines and/or sense lines, as well as the time required for sensing the data state leaked onto a bitline/senseline make a significant contribution to the overall read access time. Therefore, although conventional sense amplifiers are sufficient in some regards, the inventors have devised improved sense amplifiers as set forth herein.